Performance Analysis of Standard Quaternary Inverters for Noise Margin

The huge number of interconnections in digital circuits is the main issue in chip design. It is possible to reduce chip size and interconnections by using multi-valued logic, which leads to less power consumption. The use of multi-valued logic has the potential to improve the connection complexity, efficiency of arithmetic circuits, and digital signal processing. Because of the enormous potential of CNTFET in circuit design, several studies into multi-valued logic have been conducted in recent years. The ability of the carbon nanotube field effect transistor to have multi-threshold voltage resulted in its extensive use in designing multi-valued circuits. This study presents a performance analysis of existing standard quaternary inverters based on two definitions of noise to examine their noise sensitivity. The designs are simulated using Synopsys HSPICE with a 32nm model provided by Stanford University. The existing designs are compared in terms of power, delay, PDP, and noise margin.