Influence of Temperature Fluctuations on the Analog and RF Characteristics of Gate-Engineered High-K Gate Dielectric Stack SOI Fin-FET

The phenomenal advancement and unceasing growth of research in the area of nanotechnology have resulted to an increase in the effectiveness of gadgets at the fundamental level. The device has undergone a continuous shrink in physical size to meet the power requirement of the next-generation device. The dawn of the fin-FET changes the game by its enhanced performance in terms of short-channel effects (SCEs) where as the conventional FET device fails. In this work, we have examined the thermal stability of high-k spacer gate oxide stack silicon on insulator (SOI) fin-FET device, focusing on its impact on key electrical parameters like on drain current (
$I_{on}$
), threshold voltage (
$V_{th}$
) and transconductance (
$g_{m}$
), etc. Semiconductor device characteristics depend on biasing voltages and the temperature condition, so the device is need to be calibrated against these conditions. The High-K spacer dielectric over the channel region provides high stability for the proposed GOS-finFET against the different thermal conditions. A comprehensive investigation of the Analog and RF parameters of the finFET device was carried out by taking temperature ranges from 300K to 400K. This work also presents an insightful investigation of the electrical parameters of the finFET by including potential, energy band as well as transfer characteristics of a device which are essential for practical implementation.