An Electronically Tunable Capacitance Multiplier Structure Using DTMOS Technique for the Low Frequency Applications

In this study, a capacitor multiplier based on Multiple Output-Voltage Difference Transconductance Amplifier (MO-VDTA) is built by employing DTMOS transistors. The proposed MO-VDTA based capacitor multiplier is composed of three stages, one of which is operated in the subthreshold region. The proposed structure works with ±0.9V and ±0.3V supply voltages and can be safely tunable for the low frequency operations where the large capacitor values are needed. The proposed multiplier is tested in a 2
^nd
order low-pass filter, while the cut-off frequency of proposed filter from “12Hz” up to “40Hz” and total power consumption of the proposed filter is given around 700µW. Also, multiplication factor can be changed from “40000” to “120000” by the virtue of bias currents. In order to verify the multiplier performance, Monte-Carlo, THD and noise analysis are given in conjunction with the filter results. Performance comparison with the previous studies is presented as well.