Novel March WY Approach for Dynamic Fault Detection in Memory BIST

Dynamic fault detection has shown an increasingly important role in the DPM level for embedded memories in SoC. Memory testing is directly related to the reliability of the whole SoC since embedded memories occupy a large area in the SoC and are used to store data for application usage. However, it is essential to bring down the test complexity of the March-based test algorithm for dynamic fault detection to maintain the test time and expenses within an acceptable economic range. March WY1 (66n) is proposed as the minimal March algorithm targeting unlinked two-operation single-cell dynamic faults and double-cell faults of types Sw and Saa to enhance the test efficiency for dynamic fault detection in SRAM. The proposed March WY1 (66n) has reduced test complexity by 4n compared to the well-known March MD2 (70n) while maintaining the same 100% dynamic fault coverages.