Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip

Tiled Chip Multicore Processors (TCMP), which utilise Network on Chip (NoC) as the underlying interconnection network, are currently the foundation for modern data-intensive parallel systems. Manufacturers are examining the viability of using a range of intermediary Intellectual Property (IP) cores in TCMP designs due to rigorous time-to-market constraints. When IP is outsourced to vendors around the world, System-on-Chip (SoC) architectures are vulnerable to malicious implantations like Hardware Trojan (HT). The presence of malicious HT in NoC routers has a negative impact on the functionality of the entire system. Hardware trojans in 3D bufferless NoC is a less explored area. In this paper, we model an HT creating Push Back Attack that targets a 3D bufferless NoC router’s port allocation unit and redirects all flits going through it. We investigate the effects of such an HT and assess its impact at the network level by considering performance parameters such as average latency, deflection rate, throughput and router link utilization.