A Generic CDC Modeling for Data Stability Verification

Industrial circuits are increasing in size and complexity every day, making it very difficult to propagate one low-skew clock. To overcome this problem, and achieve a certain level of power optimization, Globally Asynchronous Locally Synchronous (GALS) systems are widely used. However, in these asynchronous multi-clock systems, some other problems arise due to clock, reset, and power domain crossing; they are the subject of different types of exhaustive verification. The goal is to detect all the Clock Domain Crossing (CDC) signals and ensure that they are properly synchronized. We have noticed some limitations related to the CDC data paths detection at RT-level by the industrial static verification tools. They fail to detect all types of synchronization protocols. We propose a new approach that does not depend on them. It is able to correctly detect all control synchronization signals.