Hardware-Efficient Random-Modulation ΣΔ ADC for Per-Column CS Generation in Vision Sensor

Compressive sensing (CS) encodes multiple projections of a signal. If the signal is an image, each projection is a linear combination of all pixels, which requires a high-resolution analog-to-digital converter (ADC). $\Sigma \Delta$ ADCs have been widely used to digitize compressed samples with practical resolution. In this study, we present the circuit-level implementation of a hardware-efficient random-modulation first-order incremental $\Sigma \Delta \mathrm{ADC}$. This ADC can perform random modulation of input signals by ±1 while simultaneously quantizing and averaging the signals. The random modulation takes place directly at the decimation filter without requiring additional circuitry, in contrast to state-of-the-art works. The ADC has been designed for per-column CS realization in a vision sensor featuring a pixel pitch of $4 \mu \mathrm{m}$. However, the scheme is general and can be employed in any other relevant CS application. All circuits have been designed using a 110 nm CMOS image sensor technology.