Simulation of Divider Phase Noise and Spurious Tones in Integer-N PLLs

Integer-N PLLs are preferred when fine frequency resolution is not required, and both phase noise and spurious tones must be maintained at very low levels. When the feedback divider’s modulus is very large, simulating its phase noise contribution can be difficult. This is because the fundamental frequency is the divider output frequency, and enough harmonics must be used to model the switching waveforms at the input frequency. A method is outlined by which the divider’s output phase noise can be accurately determined by simulating stages of the divider one at a time. Spurious tones at the reference frequency are expected in an integer-N PLL, but, when the division modulus is odd, spurs can also occur at half the reference frequency. The cause of the sub-reference spurs, as well as possible remedies, are discussed.