A Low Noise TIA with T-network Feedback Using High Value Gate Controlled PMOS Resistors

In this work, a novel low noise trans-impedance amplifier (LN-TIA) with T-network feedback, in which tunable PMOS resistors are deployed, is presented. These pseudo resistors are used to physically imitate the large value resistors which could be mostly impractical to realize on chip or costly in terms of occupied silicon area. The proposed resistors apply quasi-floating-gate (QFG) technique to mitigate nonlinearity, and also employ quasi-floating-N-well (QFNW) to isolate the well capacitance. The pseudo resistor is optimized for noise and linearity, which make it well-suited for tunable low noise TIAs. The trans-impedance (TI) gain is from 100 $\mathrm{k}\Omega$ to 125 $\mathrm{M}\Omega$, where the operating frequency is from 100 Hz up to 18.5 kHz. The chip occupies 1170 $\mu m\times 1332 \mu {\mathrm {m}}$ in a 2 Metal CMOS 0.7 μm. The TIA with its biasing circuit occupies 570 μm×715μm silicon area, excluding I/O pads.