VLSI Design for Low-power and Wide-band Programmable Frequency Divider

We developed an efficient, programmable frequency divider with minimal power requirements and a wide-band frequency range. This design adopted the pulse swallow counter, which consisted of a divide-by-4/5 prescaler, a 6-bit pulse counter, and a 2-bit swallow counter. The Extended True Single-Phase Clock (E-TSPC) flip-flops were used in an inventive low-cost divide-by-2/3 prescaler added to the divideby-4/5 prescaler. The novel divide-by-2/3 prescaler included only 12 transistors with a single modulus control. We modified the True Single-Phase Clock (TSPC) D flip-flop with a set/reset function in the pulse counter section. It saved additional logic gates and reduced hardware costs and power dissipation. Besides, synchronizing the Johnson counter as a swallow counter prevented unexpected errors during extended periods of floating states. The designed circuit was implemented on TSMC 40nm CMOS technology, and the simulation results showed that the operating frequency expanded from 4 to 30 GHz with a continuous division ratio range of 16 to 263. We observed that the maximum power dissipation was 0.324 mW when the modulus was 18 at the highest operating frequency under a 0.9-volt supply voltage. The minimum power dissipation was 0.173 mW when the modulus was 260 at 30 GHz under a 0.9 V power supply.