Gate Lifetime of P-Gate GaN HEMT Under DC and Switching Overvoltage Stress

This paper investigates the gate lifetime of Schottky-type p-gate GaN HEMTs (SP-HEMTs) under positive gate voltage $(V_{\mathrm{G}})$ stress. The VG stress is implemented in both the DC bias and the switching at various frequencies (fsw). For the switching stress, the impacts of two switching schemes, i.e., drain-and-source grounded (DSG) and inductive hard switching (HSW), on the gate lifetime are studied. The switching stress features the repetitive, resonant $V_{\mathrm{G}}$ ringing with an average $dV_{\mathrm{G}}/dt$ of 1~2 V/ns produced by a VG-overshoot-generation circuit. It is found that, in either the DC or switching case, the gate lifetime shows a power-law relation with the $V_{\mathrm{G}}$-stress magnitude and can be fitted by Weibull distribution. At $f\mathrm{s}\mathrm{w}$ up to 100 kHz, the switching lifetime is determined by the switching cycle numbers. The maximum allowable V
G
values for a 10-year lifetime extracted under the DC bias and the 100 kHz DSG switching are found to be similar (~6V). A higher V
G
limit of ~10 V is revealed under the 100-kHz HSW condition. These results provide new insights of GaN HEMT gate lifetime under static and dynamic stresses and provide useful reference for the gate qualification.