Investigation on ESD Robustness of 20-V GGNMOS and GDPMOS in 4H-SiC Process with 100-ns TLP Pulse

The ESD robustness of 20-V GGNMOS and GDPMOS fabricated by the 4H-SiC process was investigated by the 100-ns transmission-line-pulse (TLP) pulse. The experimental results show that, under the test of breakdown mode, there is no correlation between the ESD robustness and the number of fingers. However, under the test of forward mode, the ESD robustness can be enhanced effectively by increasing the number of fingers. When the ESD current is conducted in the forward mode through the body diode of GGNMOS or GDPMOS, the ESD robustness can be effectively enhanced. Hence, the concept and schematic diagram of the whole-chip ESD protection are proposed to achieve sufficient ESD robustness of SiC ICs. Furthermore, the power-rail ESD clamp is an indispensable element to achieve sufficient ESD robustness.