Microprocessor Instruction Design Tool for RISC-V Architecture

We have been developing MEIMAT (MEiji Microprocessor Architecture Design Tools). The MEIMAT is essentially designed to be able to represent any instruction of various processors by the MEIMAT meta-instruction in two ways of semantic and functional expressions. In this paper, we have verified the RISC-V support to the MEIMAT, and have improved so that MEIMAT further supports RISC-V. First, we have verified whether the RISC-V instructions can be expressed by the MEIMAT semantic expression. It is also verified that the functional expression is automatically generated from the semantic instruction, and the corresponding correct circuit diagrams are generated in the MEIMAT instruction visualization tool. Then, we have newly developed a stage configuration mechanism to implement the RISC-V instructions. Because the RISC-V architecture is implemented by 4 or 5 processing stages in most actual processors. To develop further an easy-to-understand design tool, we have also introduced illustration windows for RISC-V specified hardware modules such as a register file, especially a status register in the instruction visualization tool. Finally, through these verifications and improvements, we have successfully confirmed that the 43 instructions in the RISCV (RV32I) instructions set of the RISC-V architecture can be converted into MEIMAT meta-instructions, and then they can be represented as circuit diagrams with the RISC-V stage configuration in the MEIMAT instruction visualization tool.