AMBA AHB to APB Bridge Protocol Verification Using System Verilog

The AHB (Advanced High-performance Bus) is a member of the AMBA (Advanced Microcontroller Bus Architecture) bus family and is a high-performance, low-power, high-bandwidth bus. It serves as a paradigm for communication between the system components. Low-bandwidth peripherals are connected using the Advanced Peripheral Bus (APB). It is a straightforward, non-pipelined protocol that allows read-and-write communication between a bridge/master and a sizable number of slaves via a common bus. The AHB to APB bridge plays a crucial role in integrating different bus protocols and enabling efficient communication between high-performance processing units and slower peripherals, contributing to the overall effectiveness and functionality of the SoC. This work focuses on functional verification of AMBA AHB to APB Bridge protocol for completeness by employing System Verilog layered testbench architecture. This ensures complete verification of functionality with maximal coverage. The verification environment is created using System Verilog and the simulations are carried out on the EDA playground.