Design and Implementation of AES-SHA Security Hardware using FPGA

In cryptography, hash functions are one of the most fundamental types of cryptographic primitives. They are applied in various contexts, including signature authentication and maintaining the integrity of communications. These functions are used to obtain a fixed-size unique fingerprint or hash value for an arbitrary message length. The message length can be anything. Everyone knows the importance of data encryption to maintain the privacy and confidentiality of data transmitted over various computer networks. Advanced Encryption Standard (AES) is one of the methods used to achieve this purpose. Still, an efficient design must be implemented at high speed to keep up with technology development. The Secure Hash Algorithm-3 (SHA-3) family of binary data functions is defined in this standard. NIST's choice for the SHA-3 Cryptographic Hash Algorithm Competition was an implementation of the KECCAK algorithm, from which all SHA-3 functions are derived. This standard also specifies the KECCAK-p family of mathematical permutations, including those that underpin KECCAK. The Advanced Encryption Standard (AES) and Hash can be implemented in software or hardware. However, AES and Hash are implemented on hardware. Because hardware implementation satisfies the speed, throughput and security requirements of the complex communication systems used in modern applications, it chooses the 128-bit for this architecture in this design. There are six different algorithms in the SHA-3 family: the cryptographic hash functions SHA3-256, SHA3-384, and SHA3-512 it chooses the SHA3-256 while the throughput of the system is 64 Gbps with 50 MHz FPGA.