FPGA Implementation of Systolic Array for 2D Convolution Using Residue Number System

This paper presents an FPGA implementation of a systolic architecture for 2D convolution using the residue number system (RNS) with a designed new residue adder and residue multiplier. The proposed architecture offers improved processing speed by leveraging the benefits of RNS. Additionally, the use of a systolic array enhances parallelism, further boosting the overall performance of the convolution operation. Experimental results demonstrate the effectiveness of the approach, highlighting its potential for accelerated convolutional neural networks and real-time signal processing applications.