Hardware Efficient Edge-Detection Based Color Filter Array Interpolation for Industrial Cameras

In manufacturing and industrial inspection, digital cameras are widely used for production monitoring, warehouse management, and detecting packing defects. Digital cameras require three separate image sensors to capture full-color images. However, due to the high cost of image sensors, many digital camera manufacturers are using a single image sensor with a color filter array (CFA), thereby reducing the overall cost of the camera system. In this paper, a computationally efficient algorithm for color filter array (CFA) interpolation is specifically designed to optimize hardware resource utilization. The algorithm focuses on utilizing simple additions, subtractions, comparisons and shift operations. Furthermore, an efficient hardware architecture for the proposed algorithm is designed and modeled using Verilog HDL. It is then synthesized using the Cadence Genus compiler with 90nm Generic Process Design Kit (GPDK 90nm) CMOS technology. The results of simulations and synthesis reveal that the proposed method is computationally efficient and requires less hardware resources as compared with the existing work making it suitable for the applications mentioned above.