A Power and Area Efficient Approximate Matrix Vector Multiplier using Stochastic Computing

This paper presents a modification of the existing stochastic computing based approximate multiplier using a different stochastically generated bit stream, which results in architectural level improvements and reduced power and area consumption while maintaining computation accuracy. The power and area efficiency of different approximated multipliers (AM) and their performances are compared with those of the existing works. Later the power consumption, hardware area requirements and performance of the proposed AM based matrix vector multiplication unit is also illustrated.