Energy-Efficient and Low-Latency Optical Network-on-Chip Architecture and Mapping Solution for Artificial Neural Networks

This paper proposes an optical network-on-chip (ONoC)-based interconnection architecture and mapping mecha-nism for the artificial neural network (ANN) accelerator. Firstly, we design an ANN reshaping method to enable each processing element (PE) to compute multiple neural processes. Subsequently, an S-type mapping scheme is proposed to map the reshaped ANN onto the ONoC for data communication. The simulation results demonstrate that the proposed approach can achieve up to a 46.8% reduction in energy consumption, a 79.7% reduction in latency, and a 4.8-fold increase in throughput compared to the traditional electrical interconnection-based ANN accelerators.