BCH Implementation on Zynq-7 platform for NANDFLASH

NANDFLASH is a mass storage device for the field of aerospace intelligent control. A BCH algorithm-based error correction IP implementation for Zynq-7 platform SOC was proposed in this paper, which can achieve the ability to correct 8-bit random errors every 512 bytes. The binary operation of galois field is integrated in the IP, an eight-bit parallel encoder is realized based on the original polynomial, and an eight-bit parallel decoder is constructed by using the generated polynomial. The decoder implements verification polynomial calculation, SIBM iteration and Chien search internally, and further expands the external interface to realize algorithm engineering deployment. Simulation tests have shown that the module can correct eight-bit errors every 512 bytes.