A 6-9.3GHz Low Phase Noise Quad-Core LC VCO in 65nm CMOS

In this paper, a quad-core LC VCO design is implemented in 65nm CMOS process, with the tuning range from 6 to 9.3 GHz (45%). In this design, four identical VCO cores are coupled synchronously, which breaks through the minimum phase noise limit of a single VCO. Source inductance filtering technology is used in each VCO core to suppress the second harmonic of current source transistor injection tank. The phase noise performance of -137.7MHz is realized under the frequency offset of 1MHz at 7GHz. The VCO consumes 200mW power with the figure-of-merit(FOM) of 192.8 dBc/Hz at 1-MHz offset.