Analysis and Implementation of Staggered Wire Bonding for LVDS Data and Large Power Transmission in CMOS Image Sensors

This paper presents a novel structure of staggered pad configuration for wire bonding to simultaneously transmit Low-Voltage Differential Signaling (LVDS) data and large power for ultra-high speed global shutter(GS) CMOS image sensor(CIS). In this structure, the inner pads are high-density placed close to the pixel array to achieve large power transmission and small IR drop. The outer pads are low-density placed in the outer area of the chip with independent power ring and power pad to transmit the LVDS data and remove the interference between the CIS power line and LVDS circuit. Noise impact of power line on the LVDS signal line has been modeled, analyzed and simulated. A prototype GS CIS chip with the proposed structure has been fabricated in a 110nm CIS process. The measurement results show that the chip can provide large power of 9.7 W to the CIS and transmit LVDS data at speed of 250Mbps per channel.