A Solution Method for Non-Smooth Wirelength Model of VLSI Overall Layout Based on Neiderreit Sequence Initialized Harris Hawk Optimization

The layout method of very large scale integration (VLSI) is the top priority of its physical design and the core issue of electronic design automation (EDA) technology. It is also the most upstream, high-end and strategic part in the integrated circuit industry. The layout algorithm for VLSI typically includes3 steps: overall layout, layout legalization, and detailed layout, and the quality of the overall layout will directly affect the quality of the final layout. As overall layout is the key to the success in solving layout problems for VLSI, in this paper, the non-smooth and non-convex optimization problem formed by the non-smooth wirelength model of VLSI overall layout has been studied. Different from the existing methods in solving such non-smooth optimization problem based on subgradient descent (SubGD) method or conjugate subgradient (CSG) method, which are easy to fall into the trap of local minimum, in this paper, a. derivative-free optimization method based on Neiderreit sequence initialized Harris hawk optimization (NSHHO) algorithm has been proposed and applied. Numerical experiments have shown that NSHHO is more effective than those common methods that rely on subgradient information.