A 22-Bit 34-uW Sturdy-MASH Digital Delta-Sigma Modulator with Nested Bus-Splitting and Resolution Enhancement

In response to the power consumption and precision requirements of Digital Delta-Sigma Modulators (DDSMs) used in digital-to-analog converters (DACs), this paper proposes a sturdy-Multi stAge noise SHaping (MASH) DDSM structure based on nested bus-splitting and resolution enhancement techniques. This work utilized the TSMC 40nm CMOS standard cell and completed the logic synthesis using Synopsys Design Compiler, and its functionality and performance were verified in FPGA board. The results show that compared to state-of-the-art designs, this structure approximately saves 15% of hardware consumption and improves Effective Number of Bits (ENOB) by 2.36 bits.