A 4% Impedance Variation JEDEC Compatible ZQ Calibrator for DDR3, DDR4 and DDR5 SDRAM

This paper design and implement a common ZQ Calibration circuit, it can finish all calibration procedures within 60ns by 6 steps, and comparator is the important component in ZQ Calibrator, this paper utilizes a 10 kHz chopper to cancel the offset, and the offset is lower than 2mV after DCOC. this paper use multi voltage reference points for DDR3/DDR4/DDR5 calibration, DDR3 use 0.5*VDDQ as calibration point while DDR4/5 use 0.8*VDDQ. What’s more, DDR3 and DDR4 ZQ calibrator utilize external clock while DDR5 needs to use self-oscillator clock, so both external clock mode and internal clock mode are implemented in this paper, and the internal OSC period variation is lower than 10% by utilizing voltage and temperature compensation. Lastly, a scan test circuit is added in this design to facilitate ZQ calibrator test.