An Automated Deployment with Reconfigurable Digital Controller for SRAM-based Computation-in-Memory

Based on the computing mode of Compute-In-Memory, this article proposes a digital controller architecture for Compute-In-Memory. This architecture is based on a configurable on-chip network and a configurable kernel ARRAY, integrating mixed-signal with programmable near-memory digital computation, configurable buffering, and programmable control. The digital controller provides several fully parameterized operators that support network expansion. Control of the accelerator and end-to-end computation can be achieved by configuring the instruction register. Furthermore, this paper proposes an end-to-end neural network compiler that converts artificial neural network models in the Open Neural Network Exchange (ONNX) format into executable code instructions. Ultimately, these instructions will run on a heterogeneous embedded system composed of a microcontroller unit (MCU) and a computation-in-memory (CIM) accelerator. The instructions generated by the compiler fully leverage the configurable architecture to accomplish kernel mapping and dataflow scheduling, thereby significantly reducing the model deployment time. By accelerating the ResNet14 algorithm, the accelerator architecture can achieve a frame rate of 45 frames per second (FPS) and a peak throughput of 368.154 Giga operations per second (GOPS) at 10 MHz.