A 0.008mm2 -65dB PSR Analog-Digital Hybrid Capless LDO Using Switched-Capacitor Resistors and Frequency Detector

This paper presents the design and implementation of an analog-digital hybrid capless low-dropout voltage regulator (LDO). The analog-digital hybrid architecture gives a good balance between power consumption and performance. The area of the proposed LDO is dramatically reduced by using switched-capacitor resistors (SCR) as the feedback resistors, based on the internal clock to generate positive feedback, accelerate the system to recovery stability, and the load transient response performance is improved by adopting an auxiliary transient compensation loop. The proposed capless LDO achieves a small area of 0.008mm
²
, and a high PSR of −65 dB. In addition, it achieves 2mV/V line regulation, with an input voltage range of 2.9V to 3.5V. This design has a low quiescent current consumption of 5.7$\mu$A and a maximum output current load capability of l0mA. This design is implemented in SMIC 0.18$-\mu$m standard CMOS process.