Abstract:
This paper describes a single-loop 3rd-order continuous time Sigma Delta modulator for audio applications in 180nm CMOS technology. It uses a feedforward topology structu...Show MoreMetadata
Abstract:
This paper describes a single-loop 3rd-order continuous time Sigma Delta modulator for audio applications in 180nm CMOS technology. It uses a feedforward topology structure that employs summation ahead technology to reduce circuit power consumption. Meanwhile, it adopts the Negative-R compensation technology to compensate the non-ideal factors of the active RC integrator, and the quantizer consists of a 3-bit flash ADC with low kickback noise dynamic comparator so that improve modulator resolution. The simulation results show that at 1. 8V supply voltage, the SNDR is 109.3 dB, the power consumption is 461.8\muW, and the FOMSNDR is 185.7 dB.
Date of Conference: 20-23 October 2023
Date Added to IEEE Xplore: 25 December 2023
ISBN Information: