10GS/s 10bit Time-interleaved SAR ADC in 28nm CMOS

This paper describes the design of a I0GS/s10-bit 32-way time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) in 28nm CMOS. The ADC core consists of four slices, with one sample front end shared by eight SAR ADC in each slice. A CMOS clock distribution, a high-speed front end and digital calibration of time skew and offset error are combined to optimize the ADC’s performance. Simulation results show that the calibrated SAR ADC reaches 52.8 dB SNDR and 60.2 dB SFDR at Nyquist input. The ADC power dissipation is 157 mW, corresponding to an FoM of 44 fj/con.