A 10-bit 100-MS/s 1.2-mW Asynchronous SAR ADC with Low-power Dynamic Logic Units in 65nm CMOS

This paper presents a 10-bit 100-MS/s 1.2-mW asynchronous SAR ADC with low-power dynamic logic units in a 65nm CMOS process. To reduce power consumption, a dynamic logic cell capable of being turned off is proposed. Furthermore, a bootstrap switch is introduced to enhance linearity. The use of MIM capacitors ensures more accurate capacitance values. The ADC achieves both speed and accuracy objectives without the need for digital calibration in the background. Notably, it exhibits remarkable power efficiency. The prototype SAR ADC fabricated in 65nm CMOS achieves 40.07 dB SNR and 39.88 dB SNDR with low-frequency input while consuming only 1.2mW in total.