A 12-bit 625 MS/s Time-interleaved Pipelined ADC

This article presents a 12-bit 625 MS/s time-interleaved ADC analog-to-digital converter (ADC) that achieves an SFDR/SNDR of 64.47/59.08 dB near Nyquist rate. An input buffer with a replica capacitor is employed to effectively drive the sampling capacitor with high linearity. A bootstrapped sampling switch operating at 625 MS/s is adopted to eliminate timing mismatch and achieve high sampling linearity. Also, the pipelined ADC is utilized as the sub-ADC owing to its balance of sampling rate and revolution. The ADC is implemented in a 45 nm CMOS technology with 376 mW power consumption and a total layout area of 850μm $\times$ 590μm.