A 5.3-fJ/conv.-step Pipelined-SAR ADC with Resistance Assisted Two-Stage Dynamic Amplifier Based on Gm-Unit

This work presents a single-channel, fully dynamic SAR-assisted pipelined analog-to-digital converter (ADC) with a wide input range. The ADC employs a resistance assisted two-stage dynamic amplifier based on gm-unit to achieve outstanding residue amplification efficiency and settled-time. It has a small variation in input parasitic capacitance to achieve high linearity and leverages a bias compensation circuit to reduce the gain variation with a temperature drift. Moreover, an improved bootstrap switch with parasitic optimization, is adopted to achieve stable high sampling linearity over a large input frequency range. Based on the 28nm process, post simulation with noise shows that the ADC achieves a low-frequency SNDR of 67.4 dB and SFDR of 75 dBc at 500MS/s. Over Nyquist up to 900 MHz input, the SNDR and SFDR keep on 63.7dB and 67.6dBc. It consumes 5.1 mW from a 1V supply and occupies a area of 0.011 mm$^{2}$, leading to Schreier and Walden figure-of merit (FoM) values of 174.3 dB and 5.3 fJ/conv.-step, respectively.