An Adaptive All-Digital Phase-Locked Loop Architecture for High-Stability MEMS Temperature-Compensated Clocks

Silicon-based Micro-Electro-Mechanical Systems (MEMS) clocks suffer from temperature drift, which severely affects the stability of their output frequency. In order to obtain a high-precision and stable clock frequency, a temperature-compensated all-digital phase-locked loop (ADPLL) based on a counter structure is proposed in this paper. The system dynamically adjusts the frequency control word according to temperature changes, enabling the unstable signal with frequency deviation to be locked at 25MHz, achieving the goal of temperature compensation and realizing a high-stability silicon-based MEMS TCXO (temperature-compensated crystal oscillator) clock. The proposed ADPLL includes five customized or semi-customized digital modules: reference phase accumulator (RPA), variable phase counter (VPC), time-to-digital converter (TDC), infinite impulse response (IIR), and phase error calculator (PEC). The TDC uses a programmable divider for frequency synthesis, only performing digital quantization in the phase detection part. The output is generated by a digital control oscillator (DCO) based on the phase error. In this paper, the issue of insufficient stability of silicon-based MEMS clocks is first introduced, followed by a detailed description of the specific design of the ADPLL-based adaptive temperature compensation system. Finally, the paper presents the behavior-level modeling design of the ADPLL and the FPGA simulation.