Design of Digital Phase Interpolator for 6.25Gbps CDR Circuit

For high-speed serial interface application, a digital phase interpolator(PI) for 6.25Gbps clock data recovery circuit is designed. The digital PI consisted of two groups of inverter arrays, with a digital signal controlling the number of gating of the inverter array to achieve the phase adjustment function similar to analog PI. Additionally, an 8-phase divider with reset function has been designed to provide 8-phase input clocks with the correct phase relation to the digital PI. The digital PI has been implemented using TSMC 40nm process, with a layout area of 53um*23um Post-simulation results show that, at an operating speed of 6.25 Gbps, the output clock jitter is only 7.66ps, representing less than 0.15 UI, and with a low power consumption of only 0.59 mW.