An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis

Approximate circuits sacrificing accuracy in exchange for energy efficiency have been widely used in hardware deployment of neural networks (NNs). Approximate logic synthesis (ALS) has attracted attention due to its high efficiency in designing approximate circuits. This paper proposes a hybrid ALS based energy-efficient approximate multiplication and accumulation (MAC) unit, in which multipliers are designed by XOR-based BMF while adders are designed by CGP. Experiments show that compared to exact MAC, the proposed approximate MAC can reduce the power delay product (PDP) by 59.02% while the accuracy loss is only 0.72% in CIFAR10 using ResNet-18 and 2.22% in CIFAR100 using ResNet-50.