Error Bits Recovering in 3D NAND Flash Memory: A Novel State-Shift Re-Program (SRP) Scheme

To address serious concerns on charge-loss-related data retention in charge-trap (CT) 3D NAND flash memory, a novel state-shift re-program (SRP) scheme is proposed to recover error bits after long-term retention. Different from traditional re-program methods, the proposed scheme can avoid the degradation of low-state error bits significantly, and could proceed with no need to invoke the original data file. Based on the characterizations of TLC (3bit/cell) 3D NAND chip on a high-speed NAND chip tester, it is shown that the proposed SRP scheme can recover
$\mathbf{20}\sim\mathbf{30}\%$
error bits in the cycled blocks with a large amount of error bits.