Design and Characterization of a Novel Double-side Cooled Press-pack Packaging Structure

This paper introduces the design and characterization of a novel and cost-effective double-side cooling press-pack transistor outline (TO) package for a double-side patterned power device. The proposed package is based on the wire bond-less press-pack interconnect concept to improve package reliability. Special U ship AlN DBC and molybdenum spacer are applied to achieve excellent CTE performance and multiple pad interconnection on the double side of the chip. The ultra-low thermal resistance of 0.124°C/W is achieved by the proposed press-pack configuration. High isolation capability is also achieved to meet the requirements of a 1200V die. The electrical and thermal performance are analyzed through simulation and experiments.