Analysis and Suppression on High dv/dt Caused Crosstalk in Driving Paths of SiC Full-bridge Inverters

SiC inverters have been widely used in power conversion systems. However, due to their much higher switching speed and power density, interference caused by high dv/dt at voltage changing points in the power loop is likely to be coupled into control circuits through driving paths and threatening the integrity of driving PWM signals. This paper establishes an improved model of noise propagation in control circuits as well as feasible and effective noise suppression methods on a SiC two-level full-bridge inverter. The model is proposed based on the characteristics of driving paths that consist of gate drivers and auxiliary power supply, and the model is improved by excluding insignificant parts including sensing circuits. CM chokes and CM capacitors are inserted in driving paths to achieve noise suppression. As a result, CM currents in frequency domain are reduced by up to 30dB, and spike peaks of PWM signals in time domain are shaved by 20%. Simulation and experiment are conducted to verify the analysis and reduction methods above.