A Robust Design Method of Desaturation Protection Circuit for Silicon Carbide Power MOSFETs

Desaturation (DESAT) protection is a widely used short circuit (SC) protection method for power semiconductors. A method for the parametric design of the DESAT protection for silicon carbide (SiC) MOSFETs is introduced, substantially improving the robustness of the protection circuit under normal operation and SC fault scenarios. The approach is grounded on the mathematical modeling of the protection circuit’s behavioral constraints and performance metric - namely, the blanking time. The task of optimization is addressed by computing the worst-case (WC) scenario, providing a robust and viable solution for the passive component sizing that also factors in manufacturing tolerances. When compared to the nominal optimized solution, the WC optimized solution for the DESAT circuit substantially mitigates the potential for false-triggering during the normal turn-ON process and malfunctioning in hard-switching fault (HSF) events, all while incurring only a slight trade-off in SC response performance. Experimental results from 300V multi-pulse and SC testing of a half-bridge circuit reinforce the theoretical analysis and effectiveness of the proposed method.