Current Clamping Phenomena in Three Phase Inverter Considering Digital Implementation Effects

Dead time and inverter non-linearities introduce a high distortion in the voltage applied to the electrical machines, which reflects in the current waveforms. Although the effects of the dead time, the semiconductor devices voltage drop and of the parasitics have been widely investigated in the literature, less attention has been paid to the analysis and compensation of the current clamping phenomena.This article aims to fill this lack in the literature, examining the effects of the current clamping on the dead time compensation, both in the natural and synchronous reference frame. The analysis is extended to anisotropic machines and a general solution to the problem is proposed. A simple and easy to implement compensation algorithm is presented, capable of managing also the issues related the digital implementation at medium fundamental frequencies. Simulations show the validity of the proposed method.