Common-mode Voltage Reduction Method for Three-level Vienna Rectifiers

In this paper, a carrier-based implementation method with low calculation burdens is proposed for three-level Vienna rectifiers to improve the common-mode voltage (CMV) characteristic. First, in order to eliminate the six small vectors with high CMV magnitudes in the generated vector sequences, the limitation ranges of the injected zero-sequence component are studied under Alternative Phase Opposition (APOD) PWM. Then the solved zero-sequence component is injected to adjust the relative dwell times of the chosen small vector and medium vector in each sector for NP voltage regulation. Finally, experiments are carried out to verify the performance of the proposed method.