Acceleration of FFT Algorithm Based on Reconfigurable Computing Architecture

Embedded applications have high requirements for computing speed, power consumption, and cost. Traditional computing models cannot meet the emerging application scenarios and requirements. In computing-intensive fields, fast Fourier transform (FFT) is a key technical means, but the implementation of this algorithm requires complex computation and required to be accelerated urgently. To solve the above problems, this paper proposed a FFT hardware acceleration method based on the coarse-grained reconfigurable array (CGRA). By mapping the FFT core operations to hardware units, the calculation speed can be significantly increased. Experimental results show that the proposed FFT acceleration method is more efficient than related implementations.