Implementation of a Large Piezoresistive Sensor Array Scanning Mechanism based on Xilinx ZYNQ APSoC

The foremost complication of scanning a large sensor array is the increased number of sensors which generate large volumes of data. Hence, a suitable hardware based implementation is necessary to manage such data efficiently. We formulated a scanning mechanism for a large piezoresistive sensor array using a Xilinx Zynq device and custom developed RTL modules. The zynq device acts as the brain of the scanning mechanism issuing control signals and acquiring ADC readings. Therefore, we developed a scanning mechanism using a combination of Xilinx standard IP cores and custom made RTL modules, and deployed it in a zynq device. Performance of the implemented mechanism depends primarily on the developed adc 0 module. It inherits bulk of the functionality of the developed system. Hence, behavioral simulations were conducted on Vivado design suite with respect to data buffering capability, control signal issuance, data alignment and transmission for the adc_0 module. Subsequent overall analysis conducted on the system indicated that the developed system is efficiently functioning.