A Low Power Nonvolatile DRAM Cell based on ReRAMs

A one transistor, one resistor, and one resistive random-access-memory (ReRAM) (2T1R) nonvolatile-DRAM (nvDRAM) is presented in this work. By using the ReRAM as the storage component, the 2T1R cell overcomes the problem with capacitor scaling limitations, eliminates the need for periodic refresh, and achieves passive nonvolatility, negating the requirements for additional STORE/RESTORE operations after power disruption or when the DRAM is powered on. The READ voltage scheme utilizes two pulses; a Read pulse followed by a Restore pulse to prevent resistance drift of the ReRAM. The design is evaluated over simulations; successfully demonstrating nonvolatility and stored data stability during bitflip operations. Standard performance metrics such as the WRITE and READ delay, energy dissipation and EDP are then assessed over 22nm, 32nm, and 45nm transistor technology nodes. These measurements are then compared with existing DRAM designs; the 2T1R cell has an average lower READ delay by 4.6ps and an average higher WRITE delay by 8.78x10
³
ps which is limited by the ReRAM switching speed. The average READ and WRITE energy dissipations of the 2T1R cell are however lower by 1.19x103nJ and 1181.8nJ respectively. This is attributed to the reduction in transistor counts in the 2T1R design. The 2T1R cell also demonstrates an improvement in EDP over the compared DRAM designs.