Ternary Half Adder Using DGFET Technology for Low Power Applications

In this paper, the potential of Double Gate Field Effect Transistors (DGFETs) for designing low-power ternary half adders is explored. The issue at hand pertains to the challenges faced by deep submicron transistors, particularly drain-induced barrier lowering that can cause transistor failure. As a solution, we propose the use of DGFETs, which offer benefits in mitigating short-channel effects. We introduce a ternary half adder based on DGFETs, which demonstrates reduced power consumption, leakage, and operates effectively at low frequencies. Through comparative analysis, our results reveal that ternary adders designed using DGFETs are comparable with those without, in terms of latency, average power consumption, and leakage power. This study underscores the significance of DGFETs in enhancing the reliability and efficiency of electronic devices, though there may be potential implications in terms of average power and energy dissipation.