Self-calibration Fan-out Method Research for Heavy-ion Accelerator Timing System

The timing system for heavy-ion accelerator consists of three cascaded fan-outs transmission networks. In order to acquire the signal reaches the receiving device at the same time, we adopt the equal POF (Plastic Optical Fiber) at present. Thus, a self-calibrating signal fan-out method is designed in this paper. The hardware design of the signal fan-out includes the I/O(Input/Output) interface board and the FPGA (Field Programmable Gate Array) core board that adopts the double-width FMC (FPGA Mezzanine Card) standard interface. The I/O interface board realizes multichannel signal fan-out. The FPGA core board implements the signal self-calibration fan-out function. TDC (Time-to-Digital Converter) is employed to measure the round-trip transmission time of multi-channel fan-out signals. It calculates the time interval with the reference signal, updates the delay parameters, and utilizes the delay chain circuit to achieve high-precision signal output delays. This compensation of the time interval ensures that the timing signal reaches the accelerator equipment simultaneously.