Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure

Stress test is a common practice in the industry for accelerating latent defects and to pull in early life failures. Stress test requires voltage and temperature elevation for screening latent defects. This in turn implies that static timing analysis (STA) needs to be done at elevated voltage and temperature conditions. Timing closure at elevated voltages increases design area, power dissipation, and timing convergence effort. We present a relaxed timing closure methodology that targets timing closure in select DFT logic. Secondly, to ensure that the required switching activity needed for stress is achieved in the design, a specialized toggle monitor circuit is introduced. The toggle monitor can check for sign-of-life during stress test. Use of toggle monitor and relaxed timing closure on select DFT logic mitigates the design impact of timing closure at elevated voltages. Finally, it is observed on silicon that the stress content is applied correctly.