The FPGA Implementation of Pseudorandom Word Generation Algorithms

This paper introduces a novel FPGA-based hardware implementation of a pseudorandom word (PSW) generator. Using the FPGA reconfiguration property, the proposed approach allows you to change the algorithms and replace the online structure during the generator. The integration of embedded digital signal processing (DSP) blocks within the FPGA chip allows for the efficient implementation of the pseudorandom bit generator by leveraging fundamental operations like multiplication with accumulation at the gate level. The PSW generator's design and implementation are performed using the VHDL language and the CAD tool ISE 14.02 Foundation. The implementation is carried out on a Spartan-based series chip (6SLX4CSG225-3), and the paper provides a comprehensive analysis of the time and hardware costs associated with three different types of pseudorandom word generators. To validate the effectiveness of the designs, the simulation results are obtained using the ModelSim SE 10.1c, and timing diagrams are presented for these structures.