Notched gate MOSFET for capacitance reduction in RF SOI technology

Reduction of parasitic front-end capacitance is one of the key factors to improve the performance of RF applications. In this work, we report the development of an atypical gate architecture allowing the reduction of the source/drain overlap capacitances of a PD-SOI n-MOS transistor. After presenting the process flow and monitoring methods, we discuss the low frequency and RF electrical results such as C
OFF
, R
ON
, RF
Vmax
.