TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOS

Conservative timing margins are reserved in digital IC to resist process, voltage, and temperature (PVT) variations, causing large power waste. It can be mitigated or eliminated by in-situ error detection and correction (EDAC) [1]–[3] based adaptive voltage/frequency scaling (AVFS), which monitors some selected critical paths and reduces the supply voltage until reaching the point of first failure (PoFF) with error-correction (Fig. 1 top). However, it endures inactive-path risk due to the limited monitoring of critical paths because illegal voltage scaling may be applied when none of the monitored paths are inactivated (Fig. 1 bottom left) so that there is no timing error for a certain time. Analyzing a keyword spotting (KWS) task in a neural network (NN) accelerator as an example, the majority data of the MAC output is quite small (Fig. 1 bottom right) that its most significant bits could be inactivated for hundreds of cycles before the accumulated data reaches a large value to activate the critical paths. Thus, reducing VDD is at risk on this occasion. Therefore, we propose a compound timing detection of both data transition and critical path activation together, ensuring reliable voltage scaling in EDAC systems. It can confirm whether the timing is violated and whether the path is activated at the same time, thus providing reliable information on both timing and activation status (Fig. 1 middle).